PNI ASIC 3-Axis Magneto-Inductive Sensor Driver and Controller with SPI Serial Interface General Description The PNI (11096) ASIC is a low cost ma
PNIASICHostProcessorInterface Figure 5: SPI Port Full Timing Sequence (cpol = 0 ) Figure 6: SPI Port Timing Parameters (cpol = 0)
PNIASICHostProcessorInterface Idle Mode The PNI ASIC does not initialize in the idle mode at power-up. The PNI ASIC must be in a data-ready sta
PNIASICHostProcessorInterface PS0, PS1, and PS2 – Period Select Selects the division ratio applied to the L/R oscillator output to set the peri
PNIASICHostProcessorInterface Response Word PNI ASIC will return the result of a complete forward and reverse bias measurement of the sensor in
PNIASICPackageInformation Package Information Pin Configuration Figure 7: Pin Configuration PNICorporation133AviationBlvd.,Suite
PNIASICPackageInformation 28 Lead MLF (5 x 5 mm) Outline Dimensions Figure 8: 28 Lead MLF (5 x 5 mm) Outline Dimensions PNICorporation133
PNIASICPackageInformation 28 Lead MLF (5 x 5 mm) Tape & Reel Dimensions Figure 9: 28 Lead MLF (5 x 5 mm) Tape & Reel Dimensions PNIC
PNIASICPackageInformation Die Package Mechanical Specifications Die size is 2580 µm x 2360 µm (with scribe line). All X and Y coordinates refer t
PNIASICPackageInformation Die Package Mechanical Specifications Table 13: Die Pad Descriptions Pad Function X (mm) Y (mm) 1 VSTBY –655 96
Recommended Processing Parameters Figure 11: Lead Free Reflow Profile Table 14 Recommended Processing Parametersa Reflow Parameter Temperature
PNIASICSpecifications SPECIFICATIONS CAUTION: Stresses beyond those listed under Table 2 may cause permanent damage to the device. These are s
PNIASICSpecifications Electrical Specifications Parameter voltage and current levels Testing for the currents listed in Table 4 assume a static t
PNIASICTheoryofOperation Theory of Operation The PNI ASIC contains the entire measurement circuitry necessary to use PNI Corporation’s magneto-
PNIASICTheoryofOperation Figure 2: Forward Bias versus Reverse Bias illustrates the change between these two measurements. The actual magnetic m
PNIASICTheoryofOperation CONNECTIONS A typical connection configuration is shown in Figure 4 with the analog and digital sections of the PNI ASI
PNIASICHostProcessorInterface Host Processor Interface All accesses to and from the PNI ASIC are through a hardware handshaking, synchronous se
PNIASICHostProcessorInterface SPI Port Line Descriptions MOSI – Master Out Slave In The data sent from the master to the PNI ASIC. Data is tran
PNIASICHostProcessorInterface Hardware Handshaking Line Descriptions RESET RESET is usually low. RESET must be toggled from low-high-low. DRDY –
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